There are several protocol standards that specify the signaling mechanism that uses both a combination of a high speed signaling (usually greater than one gigabit per second “Gbps”) and a low speed signaling (usually as low as 3 megabits per second “Mbps”). Currently, a field programmable gate array (“FPGA”) may be used to talk to devices that have this protocol. Because a FPGA is reprogrammable, a single FPGA can be used to test different devices. For example, in one test the FPGA may be connected to a Universal Serial Bus (“USB’) device, a PCI Express device, or a universal flash storage (“UFS”) device. In UFS devices, the high speed signal is approximately 1.25, 2.5 or 5 Gbps. There is also a separate low speed signal in the range of 3 Mbps to several hundred megabits per second, but commonly it is between 10 and 100 Mbps.
It would be advantageous to communicate both signals through the high speed serial output of the FPGA—i.e., at 1.25, 2.5 or 5 Gbps and at 3 Mbps to hundreds of Mbps. However, the FPGA high speed transceiver that connects at those high speeds generally does not effectively communicate at the low signal speeds needed. The minimum speed of the FPGA high speed transceiver is somewhere on the order of 600 or 700 Mbps, far in excess of the low speed signal.
To address accessing the both the high and low speed signals, current testing uses an analog board between the device under test (“DUT”) and the FPGA. Shown in FIG. 1 is a currently used set-up 100 with an analog board 105 used to communicate with the DUT 110 using low signal speed signaling 115. When the setup 100 is in low speed mode the switches 120,125 are set to the low speed signaling at the DUT 110 and the low speed components 130 of the board 105. The components 130 may include analog switches, drivers, comparators and digital-analog converters. The components 130 are connected to the FPGA 135 via input/output lines 140. The lines 140 illustrated may represent multiple input/output lines. This switch configuration allows low speed signals to travel from the DUT 110 through the board 105 to the FPGA 135, and those signals are then processed by the protocol logic 145 allowing the CPU testing resources 150 to communicate with the DUT 110 using low speed signaling.
When the setup 100 is configured for high speed signaling the switches 120,125 are set to connect the high speed signaling 155 to be in connection with the high speed serial transceiver 160. Because the high speed signaling is within the bandwidth of the transceiver 160, the board 105 components 130 are not necessary and therefore are bypassed. The transceiver 160 is connected to the protocol logic 145, which is then connected to the CPU testing resources 150. This configuration allows the CPU testing resources 150 to communicate with the DUT 110 using high speed signaling.
The FPGA 135 is programmed such that the output of the FPGA 135 switches the analog board 105 via switches 120, 125 at the appropriate times between the high speed signaling and the low speed signaling. To provide the appropriate timing signals, several additional connections 160 to the FPGA 135 are needed that may not be readily available.
Setup 100 however, has several additional shortcomings. Manufacturing and maintaining a current inventory of needed analog boards is expensive. Not only is the manufacturing expensive, but the board may require several input/output connections to the FPGA that may not be readily available. So the testing equipment, including the FGPA would need to be physically reconfigured to accommodate a particular board. And the equipment would then need to be reconfigured again to change the board to enable testing of another DUT.
What is therefore needed is a solution that overcomes these deficiencies and allows connection to a DUT's high and low speed signaling so that testing can be done efficiently, and inexpensively. Additionally, the solution should allow for quick and easy modification of the testing equipment to accommodate various DUTs.